Review of IDS Develepment Methods in Machine Learning

Due to the rapid advancement of knowledge and technologies, the problem of decision making is getting more sophisticated to address, therefore the inventing of new methods to solve it is very important. One of the promising directions in machine learning and data mining is classifier combination. The popularity of this approach is confirmed by the still growing number of publications. This review paper focuses mainly on classifier combination known also as combined classifier, multiple classifier systems, or classifier ensemble. Eventually, recommendations and suggestions have also included

Integrated Vehicle Accident Detection and Location System

Many accident victim lives could have been saved if vehicle accident information could be intimated to an evergencey rescue center automatically. This paper proposes an accident detection and location system by determining the deceleration and data fusion from accelerometers and GPS. The bias, drift and noise errors of accelerometers and GPS outage limitation are overcome by integrating with Kalman filter. The test result shows the correct deceleration for accident detection and location. The proposed system will be able to overcome the limitations of GPS/IMU and save valuable human lives

Techniques of FECG signal analysis: detection and processing for fetal monitoring

Fetal heart rate monitoring is a technique for obtaining important information about the condition of a fetus during pregnancy and labor, by detecting the FECG signal generated by the heart of the fetus. The ultimate reason for the interest in FECG signal analysis is in clinical diagnosis and biomedical applications. The extraction and detection of the FECG signal from composite abdominal signals with powerful and advance methodologies is becoming a very important requirement in fetal monitoring. The purpose of this review paper is to illustrate the various methodologies and algorithms on FECG signal detection and analysis to provide efficient and effective ways of understanding the FECG signal and its nature. A comparative study has been carried out to show the performance of various methods. This paper opens up a passage to biomedical researchers, physicians and end users to advocate an excellent understanding of FECG signal and its analysis procedures for fetal heart rate monitoring system by providing valuable information to help them in developing more dominant, flexible and resourceful application

Dizajn i implementacija naponskog mjernog pojačala za RFID transponder s niskim naponom napajanja i malom potrošnjom struje

Current or voltage-type sense amplifier (SA) is the key element for sensing process of RFID transponder EEPROM. The performance of the EEPROM is influenced by the SA features like memory access time, power dissipation and the reliability. However, larger current or power dissipation put limitations on using current type SA with respect to voltage type SA. A low voltage SA with lower current consumption is presented in this research work, which is compatible with the low power applications like RFID transponder EEPROM. In this research, 0.18μm process is employed to design the low voltage SA with lower power consumption. The simulated results of the output showed that voltage type SA is able to operate under a low power supply voltage (VDD). In addition, only 32 μA current is dissipated by the modified voltage type SA during read period. Moreover, the proposed voltage type SA provides better reliability than the circuits presented in other research papers.Strujno ili naponsko mjerno pojačalo (MP) je ključni element očitanja RFID transpondera s EEPROM-om. Na učinak EEPROM-a utječu svojstva pojačala kao što su vrijeme pristupa memoriji, energetski gubici i pouzdanost. Veliki gubici struje i energije ograničavaju mogućnost korištenja strujnog mjernog pojačala u odnosu na naponsko. U ovom radu prikazano je niskonaponsko mjerno pojačalo s malom potrošnjom energije koje je prikladno za korištenje kod RFID transpondera s EEPROM-om. Koristi se proces od 0.18μm za dizajniranje niskonaponskog pojačala male potrošnje. Simulacije izlaznog napona su pokazale da naponsko mjerno pojačalo može raditi s niskim naponom napajanja. Tijekom vremena očitanja na modificiranom naponskom poja čalu troši se samo 32μA struje. Predloženo naponsko mjerno pojačalo ima bolju pouzdanost od onih prikazanih u drugim člancima

Hardware prototyping of an efficient encryption engine

An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can easily be fit into the systems that require different levels of security. A simple nested loop addition and subtraction have been used in order to implement the RSA operation. This has made the processing time faster and used comparatively smaller amount of space in the FPGA. The hardware design is targeted on Altera STRATIX II device and determined that the flexible key RSA encryption engine can be best suited in the device named EP2S30F484C3. The RSA encryption implementation has made use of 13,779 units of logic elements and achieved a clock frequency of 17.77MHz. It has been verified that this RSA encryption engine can perform 32-bit, 256-bit and 1024-bit encryption operation in less than 41.585us, 531.515us and 790.61us respectively

FPGA implementation of RSA encryption engine with flexible key size

An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can easily be fit into the systems that require different levels of security. A simple nested loop addition and subtraction have been used in order to implement the RSA operation. This has made the processing time faster and used comparatively smaller amount of space in the FPGA. The hardware design is targeted on Altera STRATIX II device and determined that the flexible key RSA encryption engine can be best suited in the device named EP2S30F484C3. The RSA encryption implementation has made use of 13,779 units of logic elements and achieved a clock frequency of 17.77MHz. It has been verified that this RSA encryption engine can perform 32-bit, 256-bit and 1024-bit encryption operation in less than 41.585us, 531.515us and 790.61us respectively

Real-time cheat-free gaming on the basis of time-stamp service

A cheat-proof protocol for real-time gaming is proposed under the assumption that time-stamp servers issue serially numbered time stamps honestly and are available near every player, i.e., they exist everywhere in the Internet. With this protocol, each player sends its action to the other player and also sends its hash to the nearest time-stamp server. The time-stamp server sends the signed hash with the time and a serial number back to the player. The actions are checked to verify that they are compatible with the hashes, and the signed hashes are checked to verify that they have the correct time and the serial numbers are contiguous. The only latency in this protocol is the travel time of the packet from one player to another. In comparison with other existing protocols, we confirm that the proposed protocol is as fast as and more secure than the fair synchronization protocol, the fastest existing protoco